Design and Verification of Dual Mode Logic (DML) for Power Efficient and High Performance

The recently proposed dual mode logic (DML) gates family enables a very high level of power delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to improve power efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the design's critical paths (CPs) and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant power consumption reduction. The proposed work is analyzed on 4bit carry skip adder, carry propagate adder, ripple carry adder and carry select adder. Simulations, carried out in a standard 180 nm dig ital CMOS process at different voltage levels VDD from 1v to 1.8v, show that the proposed approach allows performance improvement along with reduction of energy consumption, as compared with a standard CMOS implementation. KeywordsDual Mode Logic, power efficient, high performance, critical paths, power-delay optimization.